2021, issue 1, p. 86-98
Received 11.02.2021; Revised 10.03.2021; Accepted 25.03.2021
Published 30.03.2021; First Online 03.04.2021
https://doi.org/10.34229/2707-451X.21.1.9
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Twofold Addressing of Microinstructions in CMCU with Common Memory
A.A. Barkalov 1
,
L.A. Titarenko 1, 2 ,
O.M Golovin 3 ,
A.V. Matvienko 3 *
1 University of Zielona Gora, Poland
2 Kharkiv National University of Radio Electronics, Ukraine
3 V.M. Glushkov Institute of Cybernetics of the NAS of Ukraine, Kyiv
* Correspondence: This email address is being protected from spambots. You need JavaScript enabled to view it.
Introduction. Control unit (CU) is one of the most important blocks of practically any digital system. Its characteristics largely determine the characteristics of a system as a whole. As a rule, to synthesize CUs, the models of Mealy and Moore finite state machines (FSMs) are used.
The article is devoted to compositional microprogram control units (CMCUs). A CMCU is a Moore FSM in which a state register is replaced by a microinstruction address counter. The choice of CMCU is an optimal solution for implementing linear control algorithms. When developing FSM circuits, it is necessary to optimize such characteristics as the performance and hardware amount. The methods of optimization depend strongly on logic elements used. Nowadays, FPGA chips are one of the most common logic elements for implementing digital systems. To implement the CMCU circuit, it is enough to use look-up table (LUT) elements, programmable flip-flops, embedded memory blocks, and programmable interconnections.
The purpose of the article. In the article, there is proposed a CMCU design method improving such characteristics of CU as the number of logic levels and regularity of programmable interconnections.
The main drawback of LUT is a small number of inputs. Modern digital systems can generate signals of logical conditions entering the control unit, the number of which is tens of times greater than the number of LUT inputs. Such a discrepancy between the characteristics of the control algorithm and the number of inputs of the LUT elements leads to multi-level control circuits with an irregular structure of programmable interconnections, and is the reason for a decrease in performance and an increase in chip area and power consumption.
Results. A method for double addressing of microinstructions in CMCU with shared memory is proposed. The method is an adaptation of the two-fold state assignment of Mealy FSMs, the circuits of which are implemented with FPGAs. The proposed method makes it possible to obtain a microinstruction addressing circuit with two logic levels and a regular interconnection system. The paper considers an example of the synthesis of the CMCU circuit and analyzes the proposed method.
Conclusions. The proposed method allows reducing hardware amount (the number of LUTs and their interconnections), time of delay and power consumption. Moreover, the more complex the control algorithm, the greater the benefit the proposed method gives.
Keywords: compositional microprogram control unit, microinstruction, LUT, EMB, synthesis.
Cite as: Barkalov A.A., Titarenko L.A., Golovin O.M., Matvienko A.V. Twofold Addressing of Microinstructions in CMCU with Common Memory. Cybernetics and Computer Technologies. 2021. 1. P. 86–98. (in Ukrainian) https://doi.org/10.34229/2707-451X.21.1.9
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ISSN 2707-451X (Online)
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